主要學(xué)習(xí)與工作經(jīng)歷：
2009.03-2013.03 同濟大學(xué)計算機系統(tǒng)結(jié)構(gòu)專業(yè)獲工學(xué)博士學(xué)位；
2013.11-2016.11 天津大學(xué)計算機科學(xué)與技術(shù)專業(yè)獲博士后證書；
2014.01-2014.12 中國科學(xué)院計算技術(shù)研究所計算機體系結(jié)構(gòu)國家重點實驗室學(xué)習(xí)；
2005.04-至今安徽工程大學(xué)工作(博士，博士后，教授，CCF容錯計算專委，CCF集成電路設(shè)計專委，CCF高級會員)。
聯(lián)系郵箱：[email protected]； [email protected]。
研究方向：
可重構(gòu)計算系統(tǒng)編譯計算，計算機視覺，情感計算。
承擔(dān)的主要科研項目：
近年來參與或主持國家863項目、國家重點研發(fā)計劃項目、國家自然科學(xué)基金重點項目、安徽省自然科學(xué)基金面上項目、 安徽省教育廳自然科學(xué)基金重點項目等16項。
代表性科研成果：
以第一作者發(fā)表學(xué)術(shù)論文30余篇，授權(quán)軟件著作權(quán)和發(fā)明專利10項，代表性的論文列舉如下：
[01]Naijin Chen*, et al.Compute-Intensive Loop Scheduling and Optimized Mapping on CGRA [J].IEEE Transactions on Computers
(review)
[02]Naijin Chen*, Fei Cheng,Chenghao Han,Jianhui Jiang,Xiaoqing Wen.Loop Subgraph-Level Greedy Mapping Algorithm for Grid Coarse-Grained Reconfigurable Array [J].Tsinghua Science and Technology, 2023,2(28): 330-343.(中科院1區(qū)，SCI,EI)
[03]Naijin Chen*, Zhen Wang, Ruixiang He, Jianhui Jiang, Fei Cheng, Chenghao Han.Efficient scheduling mapping algorithm for row parallel coarse-grained reconfigurable architecture [J].Tsinghua Science and Technology, 2021, 26(5): 724-735.(中科院1區(qū)，SCI,EI)
[04]Naijin Chen*, Feng Zhiyong, Jiang Jianhui, He Ruixiang, Wang Zhen. Pipeline Mapping Performance Evaluation for Row Parallel Reconfigurable Cell Array [J].Journal of Tongji University(Natural Science), 2017, 45(8): 1218-1226.(EI)
[05]Naijin Chen*，F(xiàn)eng Zhiyong.Interconnect Delay Performance Evaluation for Non-Crossing Leveland Row Operands Parallel RCA[J].Journal of Tianjin University(Science and Technology),2017,50(4):429-436. (EI)
[06]Naijin Chen*,Jiang Jianhui.Mapping Algorithm of Coarse Grained Reconfigurable Cell Array for Multibranch Tree Data Flow Graph[J].Journal of Computer-Aided Design & Computer Graphics. 2016,28(7):756-766.(EI)
[07]Naijin Chen*,Jiang Jianhui. Considering Communication-Cost and Hardware-Fragment Utilization Cluster Partitioning Algorithm[J].Journal of Computer-Aided Design & Computer Graphics. 2015,27(4):754-763.(EI)
[08]Naijin Chen*,Jiang Jianhui.A Multi-Objective Optimization Mapping Algorithm for Coarse Grained Reconfigurable Architectures[J].Chinese Journal of Electronics. 2015, 43 (11):2151-2160.(EI)
[09]Naijin Chen*, Feng Zhiyong, Jiang Jianhui.Bypass node non-redundant adding algorithm for crossing-level data transmission in two-dimension reconfigurable cell array[J].Journal on Communications.2015,36(4):2015132:1-17. (EI)
[10]Naijin Chen*, Jiang Jianhui. Hardware-task partitioning algorithm merged area estimation with multi-objective optimization[J].Journal on Communications, 2013,34(2):40-55. (EI)
[11]Naijin Chen*,Jiang Jianhui,Chen Xin,Zhou Zhou,Xu Yin.An Improved Level Partitioning Algorithm Considering Minimum Execution Delay and Resource Restraints[J].Chinese Journal of Electronics. 2012,40(5):1055-1066.(EI)
[12]Naijin Chen*, Jianghui Jiang. Mapping algorithm for coarse-grained reconfigurable multimedia architectures.IEEE International Parallel&& istributed Processing Symposium (IPDPS), Shanghai, IEEE CS Press, Shanghai, China, 2012, pp. 281-286.(EI, CCF-B)
[13]Wang Zhen, Jiang Jianhui, Naijin Chen*, Lu Guangming, Zhang Ying. Effects of Thee Factors Under BTI on the Soft Error Rate of Integrated Circuits. [J].Journal of Computer Research and Development, 2018, 55 (5): 1108-1116. (EI)
學(xué)術(shù)專著
[1] 陳乃金. 可重構(gòu)計算系統(tǒng)模型資源劃分映射方法研究[M].西安：西安交通大學(xué)出版社，2023
所獲獎勵：
[1] 2006年獲安徽工程大學(xué)校級青年教師教學(xué)基本功競賽二等獎；
[2] 2009年獲安徽工程大學(xué)第12屆“教學(xué)優(yōu)秀獎”三等獎；
[3] 《平面型RTD制作過程中的兩個關(guān)鍵工藝》獲安徽省第六屆自然科學(xué)學(xué)術(shù)論文三等獎。